Data interface and high-speed communication system using the same

摘要

A data interface for communicating data between processors having: a writing-side register group in which data in a writing-side processor which transmits data is written in response to a clock signal; a reading-side register group into which the data written into the writing-side register group is transferred and written in response to a later clock operation, the data being read out by a reading-side processor of a data receiving side; a write controller for selectively writing data in a register in the writing-side register group in accordance with an address signal and a write signal of the writing-side processor; and a read controller for selectively reading data from a register in the reading-side register group in accordance with an address signal of the reading-side processor; so that a double buffer structure consisting of the writing-side buffers and the reading-side buffers causes the address signal and the data signal to individually be connected in the writing side and the reading side. Thus, the respective processors are able to transfer data without mutual interference.