发明名称 DESIGN TECHNIQUE FOR ASIC FACILITATING EXAMINATION OF SOLDERING
摘要 PROBLEM TO BE SOLVED: To provide a technique of designing ASIC which can check faulty soldering. SOLUTION: The ASIC 1 consists of an ordinary circuit 3, a selector circuit 5 which selects an output signal of the ordinary circuit 3 or an output signal of a CPU interface circuit 4, tristate buffers 6a, 6b and 6c which can regulate output of the selector circuit 5 to a high impedance, the CPU interface circuit 4 which regulates the selector circuit 5 and the tristate buffers 6a, 6b and 6c and a bus 7 which sends/receives an address and data to/from the CPU interface circuit 4. Meanwhile, ASIC 2 consists of an ordinary circuit 8, a CPU interface circuit 9 which monitors an input level of an external input circuit and a bus 10 which sends/receives an address and data to/from the CPU interface circuit 9.
申请公布号 JP2002073364(A) 申请公布日期 2002.03.12
申请号 JP20000256757 申请日期 2000.08.28
申请人 TOYO COMMUN EQUIP CO LTD 发明人 MIYATAKE ISAO
分类号 G01R31/02;G06F11/22 主分类号 G01R31/02
代理机构 代理人
主权项
地址