发明名称 |
Versatile copper-wiring layout design with low-k dielectric integration |
摘要 |
A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
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申请公布号 |
US6355563(B1) |
申请公布日期 |
2002.03.12 |
申请号 |
US20010798652 |
申请日期 |
2001.03.05 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
CHA RANDALL CHER LIANG;SEE ALEX;LIM YEOW KHENG;LEE TAE JONG;CHAN LAP |
分类号 |
H01L21/768;(IPC1-7):H01L21/44 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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