| 摘要 |
<p>PROBLEM TO BE SOLVED: To make variance in input/output phase small even under a min condition and a max condition and to make the phase margin of an inter-LSI interface large by providing a delay condition judgement part which judges a signal delay condition by itself and selecting delay values. SOLUTION: This circuit is composed of input phase matching parts 2 which are connected to input terminals for system signals such as a system clock, a timing signal, and a data signal inputted to an LSI internal circuit, output phase matching parts 3 which are connected to system signal output terminals of the LSI internal circuit 1, and a delay condition judgement part 4. The delay condition judgement part 4 judges the delay condition under which an LSI itself is operating and outputs a delay value switching control signal 5, which is supplied to all the input phase matching parts 2 and all the output phase matching parts 3. Those phase matching parts 2 and 3 select delay values with the delay value switching control signal 5 outputted by the judgement part 4.</p> |
