| 摘要 |
PURPOSE: A layout of a capacitor of a semiconductor device is provided to effectively prevent malfunction of a write/read operation caused by a short-circuit between a main lower electrode and a dummy lower electrode, and to improve yield and save money for a package process by replacing a defective cell by a redundancy cell when a bridge phenomenon between capacitors occurs in a probe test. CONSTITUTION: A plurality of memory cell regions and a dummy memory cell region surrounding the memory cell regions are defined in a semiconductor substrate. A word line is formed in the first direction of the memory cell region of the semiconductor substrate. A dummy word line is formed on the semiconductor substrate in the dummy memory cell region, in parallel with the word line. A transistor is connected to the word line. A dummy transistor is connected to the dummy word line. A lower electrode(52,53) is connected to the source of the transistor. A dummy lower electrode(50,51) is connected to the dummy source of the dummy transistor. A lower electrode connecting pattern(55,56) electrically connects the lower electrode with the dummy lower electrode.
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