| 摘要 |
PURPOSE: A stable control signal generator of an input/output sense amplifier is provided to form the input/output sense amplifier, which is operated stably in a high speed dynamic RAM. CONSTITUTION: A control portion(41) receives the first input/output sense amplifier enable signal(iosa0), an address flag signal(a_flag), and a feedback signal(N44) generated from an output portion(43) and controls an input of the address flag signal(a_flag) by generating the second output node signal(N42). The control portion(41) is formed with a plurality of PMOS transistors(PM41,PM42), a plurality of NMOS transistors(NM41,NM42), and a latch portion(42). The output portion(43) generates the second input/output sense amplifier enable signal(iosa1) in response to the second output node signal(N42) and the first input/output sense amplifier enable signal(iosa0). The output portion(43) is formed with the third inverter(INV43), a NAND gate(ND41), and the fourth inverter(INV44).
|
