| 摘要 |
PURPOSE: A shift register circuit is provided to reduce a swing width of a clock voltage applied to a shift register by installing a level shift circuit within the shift register circuit. CONSTITUTION: The first NMOS transistor(T1) is connected between the fourth node(P4i) of a previous stage(12i-1) and the first node(P1) of a stage(12i). The second NMOS transistor(T2) is connected among the first node(P1), the second node(P2), and a base voltage line(10). The third NMOS transistor(T3) is connected among a supply voltage line(8), the third clock signal line, and the second node(P2). The fourth NMOS transistor is connected between the second node(P2) and the base voltage line(10). The first capacitor(C1) is connected between the third node(P3) and the base voltage line(10). The fifth NMOS transistor(T5) is connected among the first node(P1), the first clock signal line, and the third node(P3). The sixth NMOS transistor(T6) is connected among the second node(P2), the third node(P3), and the base voltage line(10). Each level shifter(131-13n) includes the seventh transistor(T7) connected among the second clock signal line, the fifth node(P5), and the sixth node(P6), the eighth transistor(T8) connected among the fifth node(P5), a high voltage supply line(11), and the sixth node(P6), the second capacitor(CLS) connected between the sixth node(P6) and the output line(14i), the ninth transistor(T9) connected the output line(14i), the high voltage supply line(11), and a source electrode of the eighth NMOS transistor(T8), and tenth transistor(T10) connected among the output line(14i), the base voltage line(10), and a gate electrode of the seventh NMOS transistor(T7).
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