WORD LINE DECODING ARCHITECTURE IN A FLASH MEMORY

摘要

A flash memory (100) having word line decoding and selection architecture is described. The flash memory include first (202, 204) and second (206, 208) sectors of memory cells, first (201, 212) and second (214, 216) local driver circuits, first (218), second (222, 224) and third (226, 228) decoding circuits, and a driving circuit (220). A first side of decoding circuitry (218) activates a first selected plurality of local driver circuits (210, 212) and a second side of decoding circuitry (218) activates a second selected plurality of local driver circuits (214, 216). The second decoding circuits (222, 224) are coupled to the first local driver circuit. The third decoding circuits (226, 228) are coupled to the second local driver circuits (214, 216) and supply a second boosted voltage to the second selected word line. The driving circuit (220) supplies boosted voltages to the first, second and third decoding circuites (218, 22, 224, 226, 228) and the first and second local river circuits (210, 212, 214, 216).