| 摘要 |
PURPOSE: A delay locked loop(DLL) clock generator is provided, which controls a clock delay time minutely by reducing a unit delay time of a unit delay chain. CONSTITUTION: The first unit delay part(21) generates the first clock signal(CK1) by receiving an input clock signal(CKIN) in response to the first switch signal(SW1), and comprises the first inverter(INV21) inverting the first switch signal and the first and the second delay part(24,25) delaying the input clock signal by being turned on selectively by the first switch signal. The second unit delay part(22) generates the second clock signal(CK2) in response to the second switch signal(SW2), and the third unit delay part(23) generates the third clock signal(CK3) in response to the third switch signal(SW3). The first delay part comprises the second inverter(INV24) inverting the clock input signal in response to the firs switch signal, and the third inverter(INV23) inverting an output signal of the second inverter in response to the first switch signal. The second delay part comprises the fourth inverter(INV24) inverting the clock input signal in response to the first switch signal, and the fifth inverter(INV25) inverting an output signal of the fourth inverter in response to the first switch signal, and the first capacitor(C21) located between an output node of the fourth inverter and an input node of the fifth inverter and a ground power supply node.
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