| 摘要 |
<p>Magnetic tunnel junction random access memory parallel-parallel architecture wherein an array of memory cells (18) is arranged in rows and columns (15) with each memory cell including a magnetic tunnel junction (19) and a control transistor (20) connected in series. The array of memory cells is constructed with a plurality of columns and each column includes a global bit line (21) coupled to a control circuit. Each column further includes a plurality of local bit lines coupled in parallel (22) to the global bit line and a plurality of groups (16, 17) of memory cells, with each group including a plurality of memory cells connected in parallel between the local bit line and a reference potential.</p> |
