发明名称 METHOD AND APPARATUS FOR INSTRUCTION SET ARCHITECTURE TO PERFORM PRIMARY AND SHADOW DIGITAL SIGNAL PROCESSING SUB-INSTRUCTIONS SIMULTANEOUSLY
摘要 A single DSP instruction includes a pair of sub-instructions: primary DSP sub-instruction and a shadow DSP sub-instruction. The two sub-instructions are dyadic DSP instructions performing two operations in one cycle. The DSP operations include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX), and a no operation (NOP). Each signal processing unit includes a primary stage to execute a primary sub-instruction based on current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based on delayed data stored within registers in signal processing units. Control logic is used to control shadow selectors to select delayed data. The system executed DSP instrucitions by simultaneously executing primary DSP sub-instructions based on current data and shadow DSP sub-instructions based on delayed data with single DSP instruction thereby performing four operations per single instruction.
申请公布号 WO0219099(A1) 申请公布日期 2002.03.07
申请号 WO2001US25905 申请日期 2001.08.16
申请人 INTEL CORPORATION 发明人 GANAPATHY, KUMAR;KANAPATHIPILLAI, RUBAN
分类号 G06F7/52;G06F7/53;G06F7/533;G06F7/544;G06F9/30;G06F9/302;G06F9/318;G06F9/38;G06F17/10;(IPC1-7):G06F9/30;G06F9/44;G06F9/40;G06F9/52 主分类号 G06F7/52
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