| 摘要 |
The integrated memory circuit comprises a memory array and a buffer circuit (20) for receiving an external clock signal (CLKEXT), the means for transferring the clock signal, and the means for transmitting the data read in the memory array in synchronism with the leading and/or trailing edges of the clock signal pulse. The buffer circuit (20) comprises the inverter gates (I1,I2) in series as in prior buffer circuits, and in addition a front-end detector (FED) delivering an inhibition signal (INHIB) of a determined duration when the clock signal (CLK) presents a leading and/or trailing edge, a transistor-interrupter (T1) for insulating the output from the input when the inhibition signal is delivered, and a memory circuit including an inverter gate (I3) and a transistor-interrupter (T2) for maintaining a logic value at the output which is present when the inhibition signal is delivered. The inhibition signal (INHIB) is applied to the gate of the transistor-interrupter (T1) by the intermediary of an inverter gate (I4), and the front-end detector (FED) receives the clock signal from the output by the intermediary of an AND gate (21), which receives on one input the clock signal and on the other input a validation signal (VALID). The front-end detector (FED) contains a delay line with three inverter gates in series connected to the inverted input of a NOR gate, which receives the clock signal at the direct input. The first and second transistors-interrupters (T1,T2) are controlled by mutually inverted signals so that when the first is nonconducting, the second is conducting, and vice versa. The inhibition signal is transmitted only in the periods of data transmission. |
