| 摘要 |
In a lateral DMOS device 10 breakdown voltage is controlled by a voltage divider 50 coupled at opposite ends to the source 18 and drain 19. The divider node N1 between first and second resistive elements R1, R2 is connected to a second level conductive shield M2. ILD layer 34 isolates the shield M2 from first level conductive M1 contacts. |
