发明名称 |
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT HAVING MULTILAYER WIRING STRUCTURE |
摘要 |
<p>In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced. <IMAGE></p> |
申请公布号 |
EP1184901(A1) |
申请公布日期 |
2002.03.06 |
申请号 |
EP20010906202 |
申请日期 |
2001.02.22 |
申请人 |
ADVANTEST CORPORATION;SOMA, MANI |
发明人 |
SOMA, MANI;MAEDA, YASUHIRO;ISHIDA, MASAHIRO;YAMAGUCHI, TAKAHIRO |
分类号 |
H01L21/66;(IPC1-7):H01L21/66 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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