| 摘要 |
A programmable logic device (PLD) structure that combines the AND/OR structure of a CPLD with the look-up table (LUT) -based logic structure of a field programmable gate array (FPGA) to implement both wide logic functions and complex logic functions in a single pass. In one embodiment, a CPLD includes a programmable AND array, a programmable OR array, and several look-up tables (LUTs) that are connected to receive product-terms from the programmable AND array and sum-terms from the programmable OR array. The programmable AND array is programmable connected to multiple input lines, and the programmable OR array is programmably connected to receive selected product-terms generated by a group of AND gates of the programmable AND array. Each LUT includes memory cells that are addressed by the sum-term and product-term applied to the LUT input terminals.
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