| 摘要 |
A method for making an embedded DRAM structure with logic circuits having high performance salicide FETs is achieved. After forming the DRAM FETs and the logic salicide FETs, a planar first insulating layer is deposited, and contact openings are etched and filled with tungsten (W) to form FET and bit-line contacts and to form DRAM capacitor node contacts. A first metal is patterned to form the first metal interconnections including the DRAM bit lines. A second insulating layer is deposited and planarized. Openings are etched to form first vias for the FET metal interconnections and concurrently to form openings for the DRAM capacitor bottom electrodes. The openings are filled with tungsten to form W contacts in the vias and to form bottom electrodes. A thin high-k dielectric is formed over the bottom electrodes, and a second metal is deposited and patterned to form capacitor top electrodes and a second level of metal interconnections. The metal layers and the high-k dielectric layer allow low-temperature processing that is not possible with the more conventional polysilicon DRAM capacitor process. Therefore, this invention prevents salicide FET degradation due to high-temperature processing, while providing a cost-effective process.
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