发明名称 Clock generator circuit
摘要 A clock generator circuit includes an oscillation circuit which generates a first clock signal, a first timer which counts the first clock signal, a ring oscillator which generates a second clock signal, a second timer which counts the second clock signal, and a third timer that generates a third clock signal which is the output clock signal.
申请公布号 US6353351(B1) 申请公布日期 2002.03.05
申请号 US20010855512 申请日期 2001.05.16
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA;MITSUBISHI ELEC SYS LSI DESIGN 发明人 AIKAWA MINORU
分类号 G06F1/32;G06F1/04;H03L7/00;(IPC1-7):G06F1/04 主分类号 G06F1/32
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