| 摘要 |
Even when the timing signal used in the internal circuit is formed from the clock signal by the delay device, a margin to the timing signal is deleted or reduced so that operating frequency is designed as high as possible. A delay device is composed of inverters which are connected in series and time constant circuits connected in parallel with the outputs of the inverters. The time constant circuits include series circuits each having an MOS transistor and a capacitor. The change of the on-state resistance of the MOS transistor is controlled by the voltage control signal of a voltage controlled oscillator. The delay time of the internal delay device is externally controlled so that the delay time of the delay device for generating the timing signal of an internal circuit is changed. The internal circuit can be operated in a normal manner even if the operating frequency is changed to lower than usual.
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