发明名称 Ferroelectric memory
摘要 To provide a ferroelectric memory, in which data can be positively protected even in an event of fluctuations in process parameter, time can be shortened for a reliability estimation test, and it is possible to avoid device breakage resulted from the test. A source voltage VDD is detected by using a source voltage detection circuit having a stable detection level. When a detected voltage RREFA is at or lower than a set detection level VREFA, an external input terminal XEXTCE,is deactivated by using an output signal of a differential amplifier circuit to protect data. Thus, it is possible to protect data with stability.
申请公布号 US2002024839(A1) 申请公布日期 2002.02.28
申请号 US20010911831 申请日期 2001.07.25
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 MANO YOSHITAKA
分类号 G01R31/28;G01R31/3185;G11C11/22;G11C11/401;G11C14/00;G11C29/02;G11C29/06;G11C29/50;(IPC1-7):G11C11/22 主分类号 G01R31/28
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