发明名称 DIGITAL SIGNAL RECORDER AND DIGITAL SIGNAL REPRODUCER
摘要 <p>PROBLEM TO BE SOLVED: To solve such a problem that the stable recording and reproducing operations are impossible when the generation timing of the instruction from a CPU to changeover the mode is disturbed. SOLUTION: An instruction generated from the CPU 10 is fetched to a CPU instruction fetching circuit 11b after once fetched by a CPU instruction fetching circuit 11a. Then, since the operation of a forwarding head is controlled on the basis of the CPU instruction fetching circuit 11a and the operation of a backward moving head is controlled on the basis of the CPU instruction fetching circuit 11b, the operation changeover timing of the backward moving head is prevented from being earlier than the operation changeover timing of the forward head, then the satisfied recording and reproducing operations are attained.</p>
申请公布号 JP2002063751(A) 申请公布日期 2002.02.28
申请号 JP20000250802 申请日期 2000.08.22
申请人 VICTOR CO OF JAPAN LTD 发明人 KATASE WATARU
分类号 G11B5/09;G11B15/14;(IPC1-7):G11B15/14 主分类号 G11B5/09
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