| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a non-volatile memory in which memory cells which make a high speed access possible can be formed more minutely. SOLUTION: Bit lines BL and /BL are connected centering sense amplifiers S. Memory cells C (/C) are connected to these bit lines BL (/BL), respectively. A word line LWL (RWL) is connected to each memory cell (/C). When stored data in the memory cell C is at a 'H' level, a capacitor is connected between the bit line BL and the word line LWL. On the other hand, when stored data in the memory cell C is at a 'L' level, a capacitor is not connected between the bit line BL and the word line LWL. In the memory cell /C, the relation between connection of a capacitor between the bit line /BL and the word line RWL and stored data is set oppositely to the relation in the memory cell C.</p> |
