摘要 |
A memory cell array includes a normal memory cell array divided into a plurality of memory blocks, a row redundant circuit and a column redundant circuit. Independent data lines are provided for the normal memory cell array, the row redundant circuit and the column redundant circuit, respectively. A data line shift circuit selectively connects each data I/O line to a global data bus. A redundant control circuit generates a shift setting signal corresponding to the defective address for setting a connection form in a data line shift circuit when an address signal matches with a defective address.
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