Integrated circuit for testing DRAM, has judging circuit which detects normal condition of DRAM, when divided test data input for every predetermined number of bits correspond to excepted level

摘要

The test data for predetermined number of bits are stored in DRAM (202). The test data are read-out from the memory and divided for every predetermined number of bits. The divided data are input simultaneously to a judging circuit (205) which detects the normal condition of the DRAM, when the divided test data for every predetermined number of bits correspond to an expected level.