| 摘要 |
The present invention provides a semiconductor integrated circuit capable of reducing the influence of an offset voltage when amplifying and outputting a voltage in accordance with a voltage difference between first and second signal lines. The present invention includes: a PMOS transistor and an NMOS transistor composing a flip flop; an NMOS transistor for switching whether a source terminal of the NMOS transistor is connected to a ground terminal; a PMOS transistor for switching whether a voltage of a bit line is fetched to the flip flop; a PMOS transistor connected between a gate terminal of the NMOS transistor and the bit line; and a PMOS transistor connected between the gate terminal of the NMOS transistor and the bit line. Since the voltage of the bit line is adjusted in accordance with the offset voltage of the flip flop, the voltage in accordance with a voltage difference between the bit lines can be outputted without being affected by the offset voltage of the flip flop.
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