发明名称 METHOD FOR VERIFYING AND DESIGNING MULTILAYERED CIRCUIT BOARD, DEVICE FOR INSPECTING THE SAME AND DESIGNING MULTILAYERED CIRCUIT BOARD AND RECORDING MEDIUM
摘要 <p>PROBLEM TO BE SOLVED: To arrange high-speed IC in a position which is not affected by resonance in a substrate. SOLUTION: In a multilayered circuit board, a structure where a plurality of conductive layers are laminated by inserting dielectrics between the layers is installed, and electronic components are arranged on a conductive layer pattern on the outermost face at the time of mounting. At the time of inspecting the arranging positions of electronic components (high-speed IC, for example), a resonance frequency (f) between the conductive layers in the multilayer circuit board is calculated. The position of an antinode, where the amplitude change of a standing wave generated between the conductive layers, is the largest in the main face of the multilayer circuit board is calculated, based on the wavelength and the outer dimension of the multilayer circuit board at each resonance frequency (f). The specified electronic component (high-speed IC) is selected (ST9 and ST10) from the electronic components. It is investigation whether the specified electronic part is arranged in the position in a main face near the antinode of the standing wave, with respect to the conductive layer pattern on the outermost surface (ST11), and the result of investigation is outputted (ST15).</p>
申请公布号 JP2002064279(A) 申请公布日期 2002.02.28
申请号 JP20000247656 申请日期 2000.08.17
申请人 SONY CORP 发明人 ARAKI KENJI;YOKOYAMA AYAO
分类号 G06F17/50;H01L23/12;H05K3/00;H05K3/46;(IPC1-7):H05K3/46 主分类号 G06F17/50
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