| 摘要 |
The apparatus for testing a semiconductor integrated circuit using an actual operating frequency comprises a test target circuit which is to be tested and has a scan path provided in the test target circuit for executing a test. The apparatus also comprises a test pattern generation circuit which generates, after completion of the test, an HLD signal for scanning out a test result synchronously with an edge of a test clock signal with a lower frequency than the actual operating frequency, and outputs a scan-out control signal to the scan path.
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