Smartcache with interruptible block prefetch

摘要

A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit. Validity circuitry is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry is connected to the memory circuit and is operable to transfer a block of data to a selected portion of segments of the memory circuit such that a transfer to any segment within the selected portion of segments holding valid data is inhibited. A block transfer to a selected plurality of segments in the memory circuit is initiated (1600, 1624). During the block transfer, each segment is tested (1602) to detect if a segment within the selected plurality of segments holds valid data. A transfer within the block transfer to a segment is inhibited if the segment contains a valid data value (1604). Valid data can be transferred to a segment by a single data or instruction operation after a block transfer is initiated (1626). In this case, a transfer within the block transfer to the segment is inhibited if the segment contains a valid data value (1602).