发明名称 Memory latency compensation
摘要 An impact of a memory latency time on repeat operations with a memory is reduced by providing a repeat start buffer for buffering a beginning of a data sequence to be repeatedly accessed, and a repeat switching unit, connected with the memory and the repeat start buffer, for switching therebetween for accessing the buffered beginning of the data sequence to be repeatedly accessed when the data sequence is to be repeated. In case of jump operations, a further reduction is achieved by providing a first and a second data buffer connectable with the memory for buffering data sequences, and a switching unit, connected with the data buffers for switching therebetween. The memory is accessible for each data buffer during an idle memory accessing time of the other data buffer for buffering a beginning of a data sequence to be accessed successively.
申请公布号 US6351793(B2) 申请公布日期 2002.02.26
申请号 US19980137439 申请日期 1998.08.20
申请人 AGILENT TECHNOLOGIES, INC. 发明人 HENKEL THOMAS
分类号 G06F12/02;G01R31/319;G06F5/06;G06F5/16;(IPC1-7):G06F12/00 主分类号 G06F12/02
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