| 摘要 |
In case that the power source voltage rises fast, the reset signal is set in the low level when the power source is supplied, so that the PMOS transistor T1 is switched ON and the node N1 is shifted to the high level. Because the node N1 is connected to the earth line VSS through the NMOS transistor T2, the NMOS transistor T2 is switched ON when the power source voltage reaches the predetermined value. Thus, by giving a small resistance value to the resistor R1, the node N1 can shift from the high level to the low level without delay, whereby the nodes N2 and N3 are set to the high level, thereby setting the reset signal to the high level. In addition, while the reset signal stays in the high level, the PMOS transistor T1 is switched OFF to cut the current. Consequently, it has become possible to provide an integrated circuit which can save the standby current consumption and at the same time output the reset signal properly in response to the power source voltage at any rising rate.
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