Pillar process for copper interconnect scheme

摘要

A method for forming reliable inter-level metal interconnections in semiconductor integrated circuits is described where pillars are formed to connect between different metal layers. A first conductive layer is deposited overlying a substrate. A conductive etch stop layer is deposited overlying the first conductive layer and then patterned to form a mask for the fist conductive layer. This is followed by a deposition of via metal layer overlying the entire surface. A hard mask layer is deposited and patterned to form the mask where via pillars are to be formed. Subsequent anisotropic etching forms pillars in the via met layer and openings in the first conductive layer. An inter-metal dielectric (IMD) layer is deposited covering and filling both the openings in the first conductive layer and in between the via pillars. The surface is then planarized.