| 摘要 |
A plurality of testing units, each of which is applied to an input or output terminal of a device under test, are provided. An input pattern is supplied to a first testing unit that is applied to an input terminal, while expected patterns are supplied to second and third testing units that are applied to first and second output terminals, respectively. These testing units are operated in synchronism with a common clock signal. The second testing unit, which has received the expected pattern, communicates an evaluative result, indicating a point in time when the logical level of a voltage signal appearing at the first output terminal of the device under test matches with the expected pattern, to the third testing unit. And the third testing unit performs timing and functional tests on a signal appearing at the second output terminal with reference to this evaluative result.
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