| 摘要 |
A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the external address signal onto the internal address bus, and an enabling circuit for enabling a connection between the internal bus and each one of the counter stages. The enabling circuit may be driven by a true address latch enable signal. The memory counter circuit may further include a circuit for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal for driving the circuit for loading the external address signal onto the internal address bus. A signal generation circuit may also be included for generating clock signals for synchronizing each one of the counter stages. The synchronization signals are preferably not simultaneously active.
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