| 摘要 |
PURPOSE: A frequency error controller in a receiving terminal of a UMTS(Universal Mobile Telecommunication System) is provided to perform an accurate and noise-resistance frequency error controlling by using frequency error information by paths of antenna diversity common pilot channel signal as the second frequency error information by using a common pilot channel signal and an antenna diversity common pilot channel in an UMTS. CONSTITUTION: A frequency error coupler(325) inputs frequency error information of FREQ_ERROR_1(315) of a common pilot channel signal corresponding to the first path and frequency error information of FREQ_ERROR_n(212) of a common pilot channel signal corresponding to the nth path. The frequency error coupler(325) inputs locking control signal of F1-LOCK(313) of the common pilot channel signal corresponding to the first path and Fn_LOCK(212) of a locking control signal of the common pilot channel signal corresponding to the nth path. The frequency error coupler(325) inputs frequency error information D_FREQ_ERROR_1(315) of a diversity common pilot channel signal corresponding to the first path to frequency error information of D_FREQ_ERROR_n(212) of a diversity common pilot channel signal corresponding to the nth path. The frequency error coupler(325) checks whether a locking control signal of each path is in a locked state and couples the frequency error information of common pilot channel signals of paths corresponding to the locked state and the frequency error information of the diversity common pilot channel signals. A frequency error accumulator(327) accumulates coupled frequency error information outputted from the frequency error coupler(325). A digital/analog converter(329) converts the accumulatively coupled frequency error information into an analog signal and outputs it as a voltage control signal to a basic clock supplier. Thus, the basic clock supplier generates a basic clock signal by using the frequency error information reflecting the diversity common pilot channel signal by paths, that is, the reference of the second phase, and outputs the basic clock signal to a PLL that generates a carrier frequency signal.
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