NO.7 LEVEL 2 INTERFACING APPARATUS AND CONTROLLING METHOD THEREOF

摘要

PURPOSE: A No.7 level 2 interfacing apparatus and its controlling method are provided to effectively analyze a problem of a message loss and delay and prevent it in advance by additionally implementing a function of backup of a specific message and time information and a function of processing an interrupt service of MK5027 in a polling method. CONSTITUTION: An SSPA(Signaling System Processor board Assembly,100) handles a No.7 level 3 function and a signal distribution function by each link and transmits and receives a message in an HDLC(High level Data Link Control) through an IPC(Inter Processor Communication). An SSFA(Signaling System Four channel signaling terminal board Assembly,200) stores and buffers the message outputted from the SSPA(100) and checks interrupts received from each MK5027 with polling. A time switch(300) time-switches the data of the SSFA(200) and outputs it into an external interface. A main processor(200-1) stores the message output from the SSPA(100) and controls it. An MK5027(200-2) is a No.7 level 2 protocol controller. A DPRAM(Dual Port Random Access Memory)/DR(Descriptor Ring)(200-3,200-4) handle a communication between the main processor(200-1) and the MK5027(200-2). An EEPROM(Electrically Erasable and Programmable Read Only Memory)(200-5) stores a control program of the main processor(200-1). An SRAM(Static Random Access Memory) downloads a control program from the EEPROM(200-5) when a power is applied thereto, and stores a data required for performing a program. A power supply unit(200-7) supplies a power to each block. An SHW(Sub High Way) interfacing unit(200-8) handles a transmission of a message with the time switch(300). A clock distributor(200-9) supplies a clock to each block. An SMC interfacing unit(200-10) transmits and receives a message to and from an operator terminal(400) through an RS-232 cable.