| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device in which an operation frequency can be further increased. SOLUTION: This device is provided with bit lines BL0, BL1, memory cells MC1 connected to each of the bit lines BL0, BL1, and a data read-out circuit 2 connected to the bit lines BL0, BL1. This data read-out circuit 2 comprises a single end type sense amplifier circuit S/A0 receiving a potential of the bit line BL0 and amplifying this potential, and a single end type sense amplifier circuit S/A1 receiving a potential of the bit line BL1 and amplifying this potential. And at the time of reading out data, the sense amplifier circuits S/A0 and S/A1 are activated alternately synchronizing with a clock signal.
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