| 摘要 |
An output buffer circuit (300) having an output time which may be reduced is provided. The output buffer circuit (300) can include a selector (1), a precharge circuit (2) and a buffer (3). Selector (1) can be responsive to a control signal (SELB) and may provide data on a data signal line (9). Precharge circuit (2) may be responsive to control signal (SELB) and may precharge data signal line (9) to a first potential when control signal is in a disable state. Selector (1) may electrically disconnect data input terminals (4 and 5) from data signal line (9) when control signal (SELB) is in the disable state. Buffer (3) may output a logic value from the data signal line (9) when control signal (SELB) is in an enable state.
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