发明名称 |
HIGH SPEED MULTIPLE-BIT FLIP-FLOP |
摘要 |
A vertical multi-threading processor (100) includes one or more execution pipelines (200) that are formed from a plurality of multiple-bit pipeline register flip-flops (400). The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage. |
申请公布号 |
WO0215398(A2) |
申请公布日期 |
2002.02.21 |
申请号 |
WO2001US25553 |
申请日期 |
2001.08.14 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
SINGH, GAJENDRA, P.;CHAMDANI, JOSEPH, I.;RAMAN, RENU |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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