Sequential integrated circuit phase locked loop for adjusting internal clock synchronisation

摘要

The circuit has a logic circuit stage contg. a sequential logic function. A clock signal and a data signal are externally applied and are received by buffer stages. The buffered clock signal is received by a phase locked loop circuit that has the function of adjusting the synchronisation of the internal clock of the sequential circuit. This has inputs via a clock buffer circuit and a signal is fed back from one stage to the phase locked loop.