发明名称 |
Processor and information processing method |
摘要 |
A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.
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申请公布号 |
US2002023205(A1) |
申请公布日期 |
2002.02.21 |
申请号 |
US20010768363 |
申请日期 |
2001.01.25 |
申请人 |
KONDO TERUYOSHI;TAKESHIGE MASAYUKI;HIBINO SUMITAKA;ISOBE HAYATO;MIYAZAKI YUKISATO;OHARA KUNIHIRO;TANIGUCHI KAZUYA;NARITOMI HIROSHI |
发明人 |
KONDO TERUYOSHI;TAKESHIGE MASAYUKI;HIBINO SUMITAKA;ISOBE HAYATO;MIYAZAKI YUKISATO;OHARA KUNIHIRO;TANIGUCHI KAZUYA;NARITOMI HIROSHI |
分类号 |
G06F9/32;G06F9/30;G06F9/38;G06F12/04;(IPC1-7):G06F12/06;G06F9/00 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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