| 摘要 |
A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The phase comparator compares the phase of an input horizontal sync signal with that of a comparison signal. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The LPF converts the charge pump signal from the charge pump into a voltage control signal. The VCO changes the oscillation frequency in accordance with the voltage control signal output from the LPF. The 1/N frequency divider performs 1/N frequency division of the frequency signal output from the voltage-controlled oscillator in accordance with a control signal. The CRT drive circuit performs deflection processing in a CRT on the basis of an output from the frequency divider and outputs, to the phase comparator, a comparison signal based on a reference signal for a display system which is generated by CRT deflection processing. The arithmetic unit calculates a control signal to be output to the frequency divider from the horizontal sync signal. The charge pump gain of the charge pump is so controlled as to keep a PLL loop gain constant by compensating for a variation in PLL loop gain due to a change in a frequency division ratio 1/N in the frequency divider.
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