DELAY CIRCUIT AND METHOD FOR THE SAME

摘要

PURPOSE: A delay circuit is provided not to lead to an excessive increase in the delay time even if the source voltage drops, and enable to control the delay time from increasing. CONSTITUTION: A delay circuit includes an inverter chain provided with a plurality of inverters(V11-V14), a plurality of p-MOS transistors(P11,P12) and n-MOS transistors(N11,N12). The inverters(V11-VI4) are MOS devices comprised by p-MOS transistors and n-MOS transistors. Specifically, the source of each p-MOS transistor and n-MOS transistor incorporated into each inverter connected, respectively, to the power source and the ground, and each gate is connected in common to serve as the input section of the inverter, and each drain is connected in common to serve as the output section of the inverter. The p-MOS transistors(P11,P12) are connected to the output section of the inverters(V11,V13), respectively, and when a logic signal having a logic level targeted for delay is input, act as the MOS capacitor that changes from the off-state to the on-state in the transition period of the signal that appears in the output section of the inverters(V11,V13). Also, the n-MOS transistors(N11,N12) are connected respectively to the output section of the inverters(V12,V14), and when a logic signal having the logic level targeted for delay is input, acts as the MOS capacitor that changes from the off-state to the on-state in the transition period of the signal that appears in the output section of the inverters(V12, V14).