发明名称 |
Electrical circuit having inverters being serially connected together in a cascade |
摘要 |
In the case where the amplitude of the input signal is large, the duty ratio of the signal output from the last stage is greatly changed as compared with the input signal. In the present invention, in order to solve this problem, there is provided a cascade connection type inverter circuit in which the inverters at the odd-number stage is fed back to the input circuit of the inverter at the first stage via an impedance element, the circuit being characterized in that a switching means is connected for supplying to an input circuit of the inverter at the first stage a compensation current for compensating a disparity between the logical threshold value of the inverter at the first stage and the central voltage of the input signal when the voltage generated between the output terminal of the inverter at the first stage and the input terminal thereof exceeds a predetermined threshold value level.
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申请公布号 |
US2002021161(A1) |
申请公布日期 |
2002.02.21 |
申请号 |
US20010899948 |
申请日期 |
2001.07.09 |
申请人 |
MURAYAMA HIDEHISA;YAMADA HIROYUKI |
发明人 |
MURAYAMA HIDEHISA;YAMADA HIROYUKI |
分类号 |
H03G11/00;H03K5/003;H03K5/08;H03K19/0952;(IPC1-7):H03K5/08;H03L5/00 |
主分类号 |
H03G11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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