Method and apparatus for crossing clock domain boundaries

摘要

A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.