发明名称 METHOD FOR AUTOMATICALLY ARRANGING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To arrange cells and to set the driving force of each cell so as to optimize the delay of an input-output network in the automatic arrangement processing of a semiconductor integrated circuit. SOLUTION: A cell arrangement area is divided, cells are allocated to and arranged in respective divided areas (steps 201 and 202), the calculation of micro path delay in the input-output network of each cell and the temporary shift and exchange of each cell position are attempted as much as possible while the calculation of micro path delay is performed in each arrangement, cell arrangement that brings about minimum delay is decided (steps 203 to 207), the micro path delay is further performed (step 210) while the temporary switching of driving force is attempted within an arrangeable range (steps 208 and 209), and the cell is automatically arranged so as to find the driving force setting of the cell which brings about the minimum delay.
申请公布号 JP2002056042(A) 申请公布日期 2002.02.20
申请号 JP20000244335 申请日期 2000.08.11
申请人 HITACHI LTD;HITACHI SOFTWARE ENG CO LTD 发明人 SATO TOMOAKI;SHIGEGAKI MASATO;SASAKI TETSUO;MIMURA KOICHI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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