发明名称 MEMORY SUB-SYSTEM, MEMORY DEVICE, PROCESSING SYSTEM AND ACCESSING METHOD
摘要 PROBLEM TO BE SOLVED: To provide improved memory structure to realize a large capacity/ wide band width memory device and system. SOLUTION: This memory sub-system 20 is provided with a first memory bank 200a having a memory cell array 201a, a row decoder 202a to select a certain row in the array 201a and a column decoder 204a to select at least one column in the array 201a. In addition, the memory sub-system 20 is provided with a second memory bank 200b having a memory cell array 201b, a row decoder 202b to select a certain row in the array 201b and a column decoder 204b to select at least one column in the array 201b.
申请公布号 JP2002055877(A) 申请公布日期 2002.02.20
申请号 JP20010191969 申请日期 2001.06.25
申请人 CIRRUS LOGIC INC 发明人 RAO MOHAN G R
分类号 G06F12/10;G06F12/02;G06F12/06;G11C8/12;G11C11/401;G11C11/407;G11C11/408;G11C11/41;G11C11/413;(IPC1-7):G06F12/06 主分类号 G06F12/10
代理机构 代理人
主权项
地址