| 摘要 |
A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO. A scan chain can be formed by coupling the scan input SI of a first flip-flop to the scan output SO of a second, upstream flip-flop, and the scan output SO of the first flip-flop to the scan input SI of a third, downstream flip-flop.
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