Linearization of FET channel impedance for small signal applications

摘要

A system that provides a means of effectively applying a mathematical substitution to the characteristic V/I equation for FET devices operating in the ohmic region that causes the non-linear (distortion producing) term to be cancelled thereby improving the realizable channel impedance linearity by orders of magnitude. The system comprised of a means to sum an isolated specific portion of the information signal applied to the FET with the Gate controlling voltage to produce a signal value that achieves the improved linearity result when applied to the FET Gate terminal.