| 摘要 |
In a semiconductor storage device, in a CE access stage, an access operation is executed by generating a reference pulse CLK_NEW by only a signal (node A) generated through the detection of a change of the CE signal by means of a CE transition detection circuit connected to the output of a CE input circuit. An ATD signal (node D), which is generated by an ATD circuit connected to the output of an address input circuit in response to a change of an address signal after the CEa signal is inputted to each address input circuit in response to the change of the CE signal, does not contribute to the generation of the reference pulse CLK_NEW. For this reason, the reference pulse generating timing and pulse width in the CE access stage do not change from those in the address access stage, and this eliminates the lag of the access time only in the CE access stage, the lag being observed in the prior art case. In the address access stage, the signal (node D), which is generated by the ATD circuit connected to the output of the address input circuit in response to the change of the address signal, has not contributed to the generation of the reference pulse in the CE access stage, conversely becomes effective to contribute to the generation of the reference pulse CLK_NEW in the address access stage, thereby a CE access time is prevented from lagging behind an address access time.
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