发明名称 Programmable delay element and synchronous DRAM using the same
摘要 A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
申请公布号 US6348827(B1) 申请公布日期 2002.02.19
申请号 US20000501216 申请日期 2000.02.10
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 FIFIELD JOHN A.;VAN HEEL NICHOLAS M.;JACUNSKI MARK D.;CHAPMAN DAVID E.;DOUSE DAVID E.
分类号 G11C7/10;H03K5/00;H03K5/13;(IPC1-7):H03H11/26 主分类号 G11C7/10
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