发明名称 WIRE BONDING EQUIPMENT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent increase in parasitic capacitance between a word line and a bit line and increase in bit line resistivity by a method wherein, after a source/drain diffusion region is formed by an ion implantation with the use of resist as a mask, an insulator film is formed on the source/drain diffusion region by a liquid phase growth method with the use of the resist as a mask. SOLUTION: For example, in a memory cell of a flat structure, with the use of a photoresist pattern 9 as a mask, a plurality of band-like source/drain diffusion regions 1 are formed in parallel at specific intervals on a P-type silicon substrate 5 by ion implantation. Thereafter, with the use of the photoresist pattern 9 as a mask, a SiO2 film 10 serving as an insulator film is formed on the source/drain diffusion regions 1 by a liquid phase growth method. Thereby, parasitic capacitance between a word line 2 and a bit line 1 can be reduced. Further, it is possible to suppress high resistivity of the bit line 1 due to an element separation between memory cell transistors, or impurity implantation onto the bit line 1 at the time of data write.
申请公布号 JP3257940(B2) 申请公布日期 2002.02.18
申请号 JP19950320516 申请日期 1995.12.08
申请人 发明人
分类号 H01L27/112;H01L21/8246 主分类号 H01L27/112
代理机构 代理人
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